Audio-GD HE-8

Audio-GD's HE-8 is a massive R2R DAC featuring a high-end design based on very high quality components and a symmetrical architecture. It features a conversion stage based on 4 PCM1704U-K DAC chips, discrete audio circuits, Accusilicon femtosecond clocks, FPGA clock management and Class A power supplies isolated in a regenerative system.

Its main functions are as follows:

• Use of a servo-stabilised discrete power supply to power the digital circuits, ensuring extremely low noise and low operating temperature. The clock and analogue circuits are always powered by a Class A regulated power supply to achieve the best sonic results.
• Analogue sound reproduction can be selected from the front panel.
• All digital inputs and parts are isolated from the analogue parts.
• Displays the sampling rate of the input signal.
• The 10MHz clock input allows an external clock generator to be used.
• The FPGA operates using a parallel data processing mode. The I2S signal enables serial data transmission. Each bit of data requires one clock cycle. A frame of data from the left and right channels requires 64 clock cycles. Stability over 64 clock cycles is therefore necessary. Parallel mode requires only one clock to transmit and process the 32bit data from the left and right channels, which considerably improves processing speed and stability. I2S input data (USB and HDMI) is reorganised into two sets of parallel 32bit data as soon as it is input. Once the SPDIF signal has been demodulated, it too is sent to the next level of processing, via two parallel 24bit data sets. The parallel processing mode results in a clearer, more neutral sound, with better dynamics and a more analogue signature.
• The clock management design of this architecture makes the clock operation more stable, resulting in greater transparency and detailed sound.
• Analogue regenerative power supply
• The integrated regenerative power supply works like an electrical generator. It blocks most of the disturbances in the power line, providing a clean power supply to the amplifiers and reproducing neutral, analogue sound. With this architecture, the alternating current passes through the regenerative input transformer, is converted into direct current and then routed to a Class A power supply and then to the regenerative wave generator and gain stages.
• A regenerative regular wave generator produces a 50Hz wave with very low distortion that passes through the gain amplifiers and output stages. The regenerative transformers produce a clean AC power supply that feeds the separate Class A power supplies for the left and right channel preamplifiers.
• The Class A parallel connection power supply has a very high input impedance to prevent disturbances through the PSU from affecting the signal, and a low output impedance with very high speed and linearity.

DAC PCM1704U-K
The HE-8 DAC is equipped with 4 PCM1704U chips in their K version. These chips, two per channel, perform digital/analogue conversion up to PCM 32bit 384kHz in R2R within a symmetrical design, enabling the HE-8 to offer sound reproduction that's as fine as it is musical.

Optimised power supply
The HE-8 features an impressive power supply stage. It uses four high-performance R-Core transformers with a total power of 160W, as well as furthermore 60,000µF of filter capacitors to guarantee a clean and stable electrical signal. 12 sets of ultra-high-speed linear stabilised power supplies provide a separate power supply for the digital circuit, while the analogue part is served by 8 pure Class A power supplies and 4 discrete power supplies. The Class A parallel regulated power supply supplies the regenerative stage and each analogue section separately.

FPGA / CPLD
The HE-8 integrates an FPGA and CPLD in order to separate the various configured circuits and avoid interruptions. The internal components are entirely controlled by a complex software layer. A considerable advantage of using an FPGA is that it can be easily upgraded to improve the performance of the device, bringing a degree of flexibility to the device.

In the HE-8, the FPGA's high-performance SPDIF interface replaces traditional SPDIF interface chips, whose performance is inferior to that of an FPGA.

The reclocking process with FIFO design is applied to all inputs. In this way, the output data remains fully synchronised with the clock signal to reject jitter.

The HE-8 features 2x / 4x / 8x oversampling modes and built-in digital filters, as well as four different NOS modes, to suit your listening style and system. 

Technical Specifications