Audio-GD R-7HE MK3

Audio-GD is developing its HE range, composed of its most top-of-the-range products. They benefit from the longest design and testing period since the brand's inception. This R-7HE 2023 MKIII model is an updated version of the R-7HE 2023 MKII.

The excellent Audio-GD R2R 7 HE updated
Audio-GD is developing its HE range, composed of its most top-of-the-range products. They benefit from the longest design and testing period since the brand's inception. This R-7HE model is an updated version of the R2R-7-HE. It thus takes up everything that made the success of its predecessor, namely 4 Ladder DAC DA-7 R2R fully symmetrical and discreet, allowing support of the DSD512 and PCM 32Bit 384kHz in the best way. It adds to this an improvement in the isolated Class A power supply for the Amanero module, a larger display with new buttons on the front panel to be able to change the settings without opening the device and finally a Mini USB port on the rear panel to be able to easily perform firmware updates.

It also features a Field-Programmable Gate Array (FPGA) processor identical to those used in very high-end DACs, such as the popular ROCKNA WAVEDREAM DAC. On the restitution side, we also find the performances of the previous model, namely a sound rich in details, a great dynamics, and a wide and deep sound scene.

2023 Edition MKIII
The 2023 version of the Audio-GD R-27 features the same design and functions as the MKII, but with new improvements.

• New feature A more elegant chassis with a central chamfer.
• New feature A 2-line screen.
• The USB and HDMI inputs use separate isolators and an isolated power supply to avoid possible interruptions in the flow from your computer or HDMI source.
• The USB input uses a bi-directional isolator that can transmit the I2S signal to the FPGA processor and receive the clock signal from it for accurate transmission of the data stream.
• The HDMI input has its own isolator for better sound quality.
• Use of asynchronous DSD clock technology.
• The SPDIF input now supports DoP.
• The FPGA processes data in parallel mode so that only one clock cycle is required to process and transmit a data frame.
• The I2S input (including USB and HDMI input) has been combined to switch to dual 32bit parallel. The SPDIF input after decoder has been combined to dual 24bit parallel. The DSD input has been combined to dual 64bit parallel.
• Revised and improved clock configuration for better synchronization.

TECHNICAL SPECIFICATIONS